Researchers Build MRAM-Based Ising Machine to Accelerate Semiconductor Layout Optimization

Engineers from Beihang University, Suzhou Inston Technology Co. Ltd., and Empyrean Technology Co. Ltd. have developed a spintronic computing system capable of solving complex combinatorial optimization problems, including key stages of microchip layout design. The device, detailed in research published in Nature Electronics, incorporates magnetoresistive random-access memory (MRAM) into a complementary metal-oxide-semiconductor (CMOS) framework to execute probabilistic state changes at sub-nanosecond speeds.

As reported by TechXplore (https://techxplore.com/news/2026-09-magnetic-tackle-complex-optimization-problems.html), conventional computer architectures based on von Neumann models face scalability limits when calculating solutions for dense optimization tasks, such as routing interconnections and managing multi-layer wiring on integrated circuits. Ising machines offer a specialized computing approach modeled on magnetic spin interactions, using binary variable states to rapidly search through large combinations of prospective choices under set parameters.

"Physics-inspired Ising machines are a hardware alternative to traditional von Neumann architectures for solving computationally intensive combinatorial optimization problems," wrote researchers Sai Li, Yihao Zhang, and their co-authors. "They can be implemented using quantum, optical and electronic platforms, but speed and scalability are fundamentally limited by the physical mechanisms governing their spin dynamics. We report a complementary-metal–oxide–semiconductor-integrated spintronic Ising machine with sub-nanosecond probabilistic spin updates."

The experimental hardware relies on an MRAM architecture comprising 96,000 spin elements, each representing binary state values of +1 or −1. By leveraging the voltage-controlled magnetic anisotropy effect, the system maintains low electrical write currents while allowing engineers to tune the state-switching probability of individual spins from 0% to 100% through electrical pulse-width adjustments.

Performance measurements published by the team indicate spin update speeds between 0.3 and 1 nanosecond, with an energy consumption below 40 femtojoules per spin. Modulating the duration of applied electrical pulses gives the system precise probabilistic control over whether a given magnetic component flips its orientation.

To test practical applications, the authors applied the platform to electronic design automation tasks involved in chip design. Specifically, the Ising machine demonstrated an ability to map global wiring routes and assign component connections across distinct structural layers on an integrated circuit layout.

The researchers also evaluated the system using Max-cut mathematical benchmark tests, which measure hardware efficiency in dividing network nodes into two sets to maximize inter-group connections. In these evaluations, the system recorded an operational energy efficiency rate of 1.92 × 10⁵ solutions per second per watt, pointing toward potential scaling for larger industrial optimization workloads.