Waymo Unveils Custom 5nm Silicon and In-Vehicle Compute Architecture

Alphabet’s autonomous vehicle subsidiary Waymo has revealed technical details regarding the custom hardware and compute architecture mounted inside its self-driving taxis, including a proprietary 5nm application-specific integrated circuit (ASIC) designed for real-time sensor processing. Writing in technical documentation first cited by Hacker News, Satish Jeyachandran, Waymo's Vice President of Engineering, and Daniel Rosenband, Compute Lead, detailed how the company transitioned from off-the-shelf hardware to custom silicon to manage physical artificial intelligence workloads on the road.

Over the past eight years, Waymo has expanded its raw processing capacity by 20 times to meet the onboard requirements of driverless operations. The hardware architecture has been refined across more than 200 million miles of fully autonomous driving experience, moving beyond conventional driver-assist compute models to handle complete vehicle control without a human safety driver present.

To ensure physical vehicle safety, Waymo engineered its compute stack around three core design principles: responsiveness, ruggedness, and architectural redundancy. The system relies entirely on onboard execution to compute driving choices within milliseconds, minimizing latency from initial sensor pixel capture to mechanical actuation. Additionally, the computing unit connects directly into the vehicle’s liquid cooling loop to sustain performance in extreme heat environments like Phoenix or freezing winter conditions in the Midwest, while using a dual-engine architecture where two parallel computing units can seamlessly take over if an internal fault occurs.

At the center of the updated hardware design is Waymo’s custom-built 5nm ASIC, an accelerator engineered specifically to fuse and analyze raw sensor streams before feeding core machine learning algorithms. The specialized chip provides over 1,000 trillion operations per second (TOPS) of dedicated machine learning performance for front-end execution, allowing the system to run diverse AI model types ranging from sparse convolutions to dense transformer networks.

The custom silicon acts as a front-end processing powerhouse, simultaneously ingesting high-fidelity data streams from 13 high-resolution cameras, alongside radar and lidar inputs. Built-in acceleration capabilities include temporal denoising, which cleans up visual noise to improve perception during low-light driving scenarios while maintaining bandwidth efficiency and quantization across all sensory channels.

Beyond its custom ASIC, Waymo maintains a heterogeneous computing layout to divide workloads efficiently across the vehicle. Machine learning hardware operates alongside central processing units (CPUs), graphics processing units (GPUs), and secondary accelerators. This functional separation allows dedicated non-ML responsibilities—such as task orchestration, internal data movement, and vehicle logging—to run without consuming operational cycles reserved for machine learning inference engines.

The self-driving unit’s hardware expansion relies on manufacturing and design collaboration with major semiconductor and tech supply chain vendors. Waymo explicitly credited several key industry suppliers in its hardware overview, including TSMC for chip fabrication, along with AMD, Micron, Nvidia, Samsung, Sandisk, and Socionext for complementary processing, memory, and infrastructure components.

Waymo indicated that as its underlying AI models advance and its commercial footprint expands, demand for low-latency, high-efficiency onboard hardware will continue to increase. The company plans to share further technical details regarding its hardware stack during upcoming engineering presentations at the Hot Chips conference.