UT Austin and TSMC Test Low-Power Magnetic Memory Designed for Edge AI Hardware

Researchers from the University of Texas at Austin, in collaboration with Taiwan Semiconductor Manufacturing Company (TSMC), have fabricated and evaluated an emerging magnetic memory architecture designed to lower the operational energy demands of artificial intelligence computing. The joint effort successfully tested spin-orbit torque magnetoresistive random-access memory (SOT-MRAM), a non-volatile memory system capable of preserving stored data when power is removed while executing operations faster and with significantly less electricity than traditional memory alternatives.

The ongoing expansion of artificial intelligence infrastructure and energy-intensive data centers has led to a sharp rise in electricity consumption worldwide. In Texas, which is projected to become the primary data center hub in the United States, statewide power consumption could scale up to fivefold in the coming years. As first reported by TechXplore, advances in specialized hardware like SOT-MRAM offer a potential path toward curbing this surge by improving on-chip computational efficiency and reducing reliance on cloud computing facilities.

Unlike conventional memory hardware, SOT-MRAM uses magnetic characteristics to store data. While engineers previously overlooked binary magnetic memory for artificial intelligence workloads due to its limitation of holding only two physical states—a zero or a one—the research team engineered the hardware configuration to retain computational accuracy while utilizing a simplified binary state model.

During experimental evaluations, the wafer-scale SOT-MRAM hardware was subjected to diverse artificial intelligence workloads, including neural network inference, binary neural network training, and probabilistic graph modeling. The memory chips completed individual write operations—switching stored data between binary states—in just two nanoseconds while drawing two picojoules of energy per operation. In contrast, existing memory technologies can require five to hundreds of times longer to complete write tasks, with latencies stretching into several milliseconds and energy consumption reaching hundreds of picojoules or more.

Sam Liu, the primary author of the paper published in Science Advances and a recent doctoral graduate from UT Austin, highlighted that the design overcomes longstanding hardware constraints in low-power computing environments. "The unique combination of speed, energy efficiency and endurance makes SOT-MRAM perfectly suited for AI applications, especially in devices where resources like power and memory are limited," Liu said. "SOT-MRAM hasn't been considered for AI hardware since it can only hold two states, but we designed it so we can take advantage of the binary state while still being accurate."

By delivering low latency and minimal energy draw directly on the chip, SOT-MRAM could allow edge devices such as industrial sensors and autonomous robotics to process machine learning computations internally rather than transmitting data to remote server clusters. Jean Anne Incorvia, an associate professor in the Cockrell School of Engineering's Chandra Family Department of Electrical and Computer Engineering and the faculty lead on the project, noted that the architecture could replace standard central processing units currently used in edge hardware.

"We show that SOT-MRAM AI accelerators can provide energy efficiency, with enough accuracy, to eventually replace CPU-based AI accelerators in edge devices such as sensors," Incorvia said. "For example, take a robotic hand that senses heat. Just like a human, the local AI in the hand can make a quick decision with enough accuracy to move the hand without even transmitting the neural signal to the brain. When very high accuracy is needed, then the robot can connect to GPU-based data centers in the cloud."

Following the initial testing phase, the researchers plan to focus on refining the material and physical characteristics that govern the hardware's speed and energy savings. The team also aims to address manufacturing variations across individual chips on a wafer, as device discrepancies can introduce errors that lower overall neural network accuracy.