Deconstructing Spacelab's 1980 Magnetic Core Memory Architecture

A detailed technical teardown of the computer hardware powering the 1980s Spacelab orbital laboratory has highlighted the sophisticated engineering behind late-era magnetic core memory. Built as a joint European initiative for NASA's Space Shuttle program, Spacelab relied on French-built Mitra 125 MS minicomputers rather than the shuttle's primary IBM AP-101 systems. For main storage, the system utilized 128 kilobytes of magnetic core memory composed of minute ferrite rings rather than silicon-based memory chips, according to an architectural analysis first reported by Hacker News.

Housed within the Space Shuttle’s cargo bay, Spacelab comprised a pressurized cylindrical cabin linked to the orbiter crew cabin by a tunnel, alongside external pallets carrying scientific payloads. To manage operations and experiments, the system incorporated three identical Mitra 125 MS units: one designated for overall facility management, a second handling experimental instrumentation, and a third functioning as an active redundancy backup. The computer’s magnetic core memory assembly accounted for approximately one-third of the total chassis volume. Engineered to slide out along a removable side panel, the conduction-cooled unit relied on a seven-board stack—consisting of four core planes flanked by driver boards and an interface board—interconnected via dual 160-pin connectors on side daughterboards.

The reliance on core memory in space systems reflects a pivotal era in computer history. During the late 1940s and early 1950s, early computing platforms relied on acoustic delay lines in mercury, cathode-ray tube displays, or rotating magnetic drums, all of which presented severe performance and reliability bottlenecks. Following World War II, researchers adapted special German magnetic alloys that exhibited bistable polarity flipping, enabling random-access binary storage. Jan Rajchman of RCA noted at the time that the material's application to memory was self-evident. Subsequent patent filings by independent inventor Frederick Viehe, Harvard's An Wang, RCA's Rajchman, and MIT's Jay Forrester triggered extensive legal disputes. IBM ultimately resolved the claims by paying $400,000 to Wang—who funneled the capital into founding Wang Laboratories—and $13 million to MIT, where Forrester had spearheaded the first operational core memory for the Whirlwind computer in 1953.

At its core, magnetic storage depends on tiny toroidal rings that hold a binary state through clockwise or counterclockwise magnetization induced by threaded conductive wires. To avoid individual wiring for every bit—which would require more than 100,000 leads for a 16-kilobyte array—engineers implemented coincident current addressing. Arranging cores in a two-dimensional grid allowed X and Y drive lines to carry half the current required to alter a core's magnetic state. Due to the magnetic hysteresis of the ferrite material, only the core positioned at the active wire intersection experienced the full threshold current necessary to flip its magnetic orientation. Reading stored values involved energizing intersection wires to force a zero state, inducing a brief electrical pulse in a dedicated sense wire if the core previously held a one. Because this read process erased the stored bit, memory controllers immediately executed a rewrite cycle to preserve data integrity.

To process complete computer words simultaneously, individual core planes were layered into three-dimensional stacks sharing common X and Y drive signals while maintaining isolated sense lines for each bit position. During write operations, specialized inhibit lines ran parallel to X drive wires in reverse orientation, canceling out magnetic fields on specific planes to retain zero values where required. Furthermore, because drive wires required fast, bidirectional electrical pulses reaching roughly 600 milliamperes, systems employed diode matrices to minimize driver circuitry expenses. By pairing drivers across opposite matrix ends, N drivers per side could control N^2 select lines and N^4 total cores, with dual directional diodes on every wire preventing parasitic electrical sneak paths—a design paradigm also seen in NASA's Saturn V Launch Vehicle Digital Computer.

While early core planes required painstaking manual fabrication—such as the 40 hours needed to weave a 64-by-64 grid for the Whirlwind computer—subsequent industrial automation by vendors like IBM drove costs down by half every two years, paralleling the cadence of Moore’s Law. By the time Spacelab's Mitra computer was constructed in 1980, core memory had reached its technical zenith in density and performance. The Spacelab system housed its 128 kilobytes of non-volatile RAM across four specialized boards, each holding 16,384 words of 18 bits. Beyond 16 standard data bits, each word contained a parity bit for error checking and a storage protect bit to enforce word-level write protection, allowing flight software to remain permanently stored in memory across power cycles.

Each of the four Spacelab core plane assemblies integrated 294,912 lithium ferrite cores arranged across 1,024 vertical Y wires and 288 horizontal X wires. The individual ferrite cores measured approximately 32 mils (0.8 millimeters) in outer diameter—matching dimensions found in IBM System/360 mainframes—but were packed with significantly tighter spacing. To mitigate signal noise across the high-density grid, each board split its 18 bit planes across 36 distinct green-enameled sense lines, which routed through four board pass-through holes before soldering to rear terminals. The copper X and Y drive lines were woven through the cores, with Y lines executing U-shaped dual passes through the plane matrix, representing one of the most compact implementations of magnetic core technology produced prior to the complete industry transition to semiconductor RAM.